1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) pin configuration (top view) 1 fin1 gnd cps si le fin2 sleep1 sleep2 pd1 vcc xin xout xbo pd2 lock gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 description the M64811AGP is a 1.1ghz/500mhz band two-system one-chip pll frequency synthesizer . using a high performance bi-cmos process , the product contains one two-modulus (1/32 and 1/33) prescaler that accepts inputs up to 1.1ghz and another two-modulus (1/16 and 1/17) prescaler that accepts inputs up to 500mhz ,thus helping make the equipment compact . features ?operating supply voltage : 2.7v~3.6v ?operating temperature : -30 c~+85 c ?2 pll systems (1.1ghz and 500mhz) are on one chip . pll1 : 700mhz~1.1ghz pll2 : 100mhz~500mhz ?low power consumption (icc=8ma typ at vcc=3v) . ?dividing ratio setting ranges : fin1 for 1.1ghz vco?????n(vco1)=1,024~131,071 fin2 for 500mhz vco?????n(vco2)=256~131,071 osc for fref ?????????????n(fref)=5~2,047 ?each loop has input pin for sleep mode . power supplies to 2 loops can be independently turned on/off . also can be controlled by the serial data . (when sleep1 and sleep2 is "h" . ) ?the pll standard oscillation circuit can adopt a b-e colpitts type oscillation circuit to from a stable oscillation circuit. ?current controlled charge pump . (icp= 2ma const.) ?locked condition detecting output if a phase difference smaller than 3 times ( d t) of the osc period continues for 15 periods or longer , the condition is judged as locked, and the lock terminal goes to "l" . (when , for example , fosc=19.2 mhz , d t=156 ns) ?pll lock/unlock status indicate function . (judged in the system turned on if the other system is turned off . ) ?small package (16pin ssop, lead pitch : 0.65mm) application digital cordless phone (ct2) ?digital cellular phone (pdc)
1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) 2 block diagram sleep1 latch select osc shift resister sleep control cps si fin1 xout xin fin2 pd2 vcc pd1 le gnd lock 1.1ghz 2-modulus prescaler (1/32, 1/33) 500mhz 2-modulus prescaler (1/16, 1/17) data latch swallow / programmable counter charge pump sleep2 pll2 on/off xbo 3 4 1 13 14 12 6 7 8 pll1 on/off 10 gnd programmable reference counter data latch swallow / programmable counter data latch lock detector phase detector lock detector phase detector 2 11 5 charge pump 16 9 15 lpf vco lpf vco tcxo
1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) pin no. pin identification description 1 2 3 4 7 8 9 10 11 12 14 16 fin1 vcc input from the vco , fmax = 1.1ghz . power supply . vcc = 2.7~3.6v . 6 gnd ground . cps clock pulse input . shift register clock input pin . 5 si shift register data input pin binary serial data input . le load enable input . when le is high , data stored in the shift registers is loaded into the appropriate latch . pll1 power control . "h" = normal operation , "l"=power down . pll2 power control . "h" = normal operation , "l"=power down . sleep1 sleep2 fin2 input from the vco , fmax = 500mhz . pd2 charge pump2 output . tristate output . high z when pll2 power is off . 13 gnd ground . lock when loops are locked "l" , when one of loops is unlocked"high z" . if one loop is sleep mode , the status of the other loop is checked for judgment . 15 xbo xout crystal oscillator input . xin pd1 charge pump1 output . tristate output . high z when pll1 power is off . buffer output of oscillator . function description of pins 3
1.1 g h z /500m h z d u a l p ll fr e q u e n c y s y n t h e s i ze r f o r d i gita l c e l l u l a r p h on e m 648 11 ag p m i t s u bi s hi i cs ( co m m un i c at i o n) msb msb msb 3.bit configuration of shift register shift register data latch setting power on/off setting 2 0 function description 1.data input note 1) at the leading edge of the cps input , the status of the si input is written into the shift register . note 2) the bit just before le becomes "h" is lsb , and si before msb becomes invalid . note 3) when le is "h" , the data stored in the shift registers is loaded into the appropriate latch . 2.input signal timing valid data l e msb lsb 10 dividing ratio of reference counter for reference frequency dividing ratio of swallow counter dividing ratio of programable counter for local oscillator 1 dividing ratio of programable counter for local oscillator 2 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 lsb * invalid invalid invalid invalid dividing ratio of swallow counter s i cps l e s i cps d1 d2 d19 d20 d21 d22 t su t h t cr t rh t wh t wl tsu=th=twh=twl=0.1 m smin. tcr=trh=0.1 m smin. 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 d a d b d c d d d e 2 0 2 1 2 2 2 3 2 4 2 0 2 10 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 11 2 0 2 1 2 2 2 3 2 0 2 10 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 11 2 12 ** ** * ** * hh lh hl 2 4
1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) note 5) d d and d e are used to select latched data to be updated. on;power on , off;power off note 4) power on/off control of pll system is set by d a , d b , and d f . d d d e data description 0 1 0 0 1 11 0 unused. data latched for local oscillator 1 is updated. data latched for local oscillator 2 is updated. data latched for reference frequency . external control pin serial data d a d b d c description pll1 pll2 l l * * * off off l h 0 0 * off on xbo on on osc on on sleep1 sleep2 hh 000 off off hh 001 off off hh 010 off on hh 011 off on hh 100 on off hh 101 on off hh 110 on on hh 111 on on off on off on off on off on off on on on on on on on l h 0 1 * off off on on l h 1 0 * off on on on l h 1 1 * off off on on h l 0 0 * on off on on h l 0 1 * on off on on h l 1 0 * off off on on h l 1 1 * off off on on 5
1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) note 6) dividing ratio of the reference counter for reference frequency is given by 11-bit binary coads . n(fref1)=5~2047 note 7) dividing ratio n(vco1) of vco1 for local oscillator1 is given by 5-bit swallow counter and 12-bit programable counter . n(vco1)=32 x m+a (a 1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) 4.charge pump and lock detection reference frequency(fref) divided output of local oscillator (fvco/n ) charge pump output lock output "source" "sink" "hiz" 123 15 5.sleep mode input by status of sleep1 and sleep2 , each pll can be selected to either sleep mode ( power supply is turned off . ) or operation mode . if sleep input is "h" , the pll becomes normal operation mode . ( power supplies to turn on/off can be controlled by the serial data ; submit to note 4 . ) if sleep input is "l" , the pll becomes sleep mode . ( power supply is turned off . ) 7 note 9) if the phase of divided local oscillator output (fvco/n) is behind that of the reference frequency (fref) , the charge pump output becomes "source" status , if advancing , "sink" status . note 10) if a phase difference smaller than 3 times of the osc period continues for 15 periods longer , the lock output becomes "l" . ( when , for example , fosc = 19.2 mhz , d t = 156 ns) note 11) if one of the power supplies to plls is turned off , a judgment is made based on only the condition of the other loop . note 12) the lock output circuit yields an open drain n-channel transistor output . it should be pulled up to vcc .
1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) input / output circuit diagram 12 3 4 5 prescaler input(fin1,fin2) si,cps 1.1ghz/500mhz dual pll frequency synthesizer for digital cellular phone M64811AGP mitsubishi ics (communication) electrical characteristics (ta= 25 c, unless otherwise specified . ) symbol parameter test condition unit limits min. max. i pd- source charge pump output (source) current 2.0 ma supply current icc1 vcc=3v , both plls are on . icc2 ma typ. pin pd1 , pd2 vcc=3.0v , v pd =vcc/2 i pd- sink charge pump output (sink) current -2.0 vcc icc3 icc4 vcc=3v , only pll1 is on . vcc=3v , only pll2 is on . vcc=3v , both plls are off . m a 8.0 5.5 4.5 10 absolute maximum ratings (ta= -30~85 c, unless otherwise specified . ) symbol parameter test condition unit ratings min. max. vcc supply voltage gnd=0v -0.3 4.5 v v i input voltage si , cps , le pin : gnd=0v -0.3 4.5 v v o output voltage output pin : gnd=0v -0.3 4.5 v pd power dissipation ta=85 c ( allowable dissipation of package ) 250 mw vopd open drain voltage gnd=0v -0.3 4.5 v topr operating temperature -30 85 c tstg storage temperature -40 125 recommended operating conditions (ta= -30~85 c, unless otherwise specified . ) symbol parameter test condition unit limits min. max. vcc supply voltage 2.7 3.6 v fin1 operating frequency vcc=2.7~3.6v 0.7 1.1 ghz fin2 100 500 mhz vin1 input sensitivity 2 dbm vin2 fin2=100~500mhz -16 -4 v xin 0.4 1.0 vp-p vcc=2.7~3.6v typ. fin1=1.0~2.0ghz -10 oscillator sensitivity @ @recommendation : x'tal (19.2mhz) handling precautions 1. this ic contains fine structure components to achieve high performance . therefore , take extra precaution to protect the ic from surge voltage caused by static electricity . 2. if one of two plls is not used , please make power supply of that turn off . c 9
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